Timing delay of reading from second RAM in FPGA.

Hi all, I have a question that has been bothering me for almost a week and hopefully someone could help me out.

Here is my plan, there are 2 RAMs in FPGA, one receives data from HPS, call it RAM0, then the output of RAM0 is added 2 and then sent to RAM1, RAM1 receives it and sends it back to HPS.

The logic is very simple here, however the timing of RAM reads and writes is really a headache to me. Now I'm using tcl file to test through System Console.

If I write the data of 88, 77, 66, 55, 44, 33, 22, 11 to address[0] -- address[7] in the RAM0, then add 2 to each elements, and then store the added data in the RAM1, the output readdata from RAM1 is 13, 8A, 79, 68, 57, 46, 35, 24 from adress[0] to address[7]. You can see that every element is added by two but the value of address[7] in RAM0 is written into address[0] in RAM1, the value of address[0] in RAM0 is written into adderss[1] in RAM1, etc. I've tried several ways to adjust the timing but it still doesn't work. The code and the System Console results have been attached.