Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- I made these hypothesis to explain the behaviour: - OS uses OS_ENTER/EXIT_CRITICAL macros which sometimes disable IRQs for a while --- Quote End --- This is definitely so, the others, not so much. Once upon a time, on another processor (far, far away) I changed the behavior of the OS_ENTER/EXIT_CRITICAL to not disable all interrupts, but masked all except my own high priority timer interrupt. This was for just the reason you are seeing. You have to be sure to save/restore everything you use, and you can't use any main program or operating system variables/services/etc., but it gets you interrupts that only jitter by the time of the longest instruction (CISC processors have variable instruction times). Another option would be to just read a free-running counter in the interrupt. Even though the interrupt is not time consistent, the free-running counter would let you know what time it is, or you could then stall in the ISR till a time reachable by all possible jitters finally arrives.