Check out the full featured designs in the examples folder of the Nios II install (assuming you have 5.0). It shows how to populate the instruction memory by dual porting it (downloading code requires that an avalon data master or tightly coupled data master be connected to the memory).
<div class='quotetop'>QUOTE </div>
--- Quote Start ---
I want to use Tightly coupled memory to replace instruction cache in my system(since my code is very small <12k). I am running a program wich is small so I can run it inside the FPGA. The purpose is to increase performance.[/b]
--- Quote End ---
Are you removing the instruction cache altogether? If you do that then the instruction master will be removed. Since tightly coupled memories are used with a 1:1 connection you would not be able to connect the tightly coupled instruction master to the memory, and have the jtag debug module connected to it as well.
My advice to you is leave a tiny amount of instruction cache behind so that your debug module will have an avalon instruction and data master to connect to. Have your tightly coupled instruction memory connect to the tighly coupled instruction master (and have the avalon data master connect to the second port). Then when all your code is debugged and ready to ship remove the debug core, the second port on the tightly coupled instruction memory, and the instruction cache to get a bit more performance out of your system (since your fmax may go up a little bit).
Honored Contributor
