Tightly Coupled Memory

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originally posted by shmueld@Jul 5 2006, 08:29 AM

i am developing a custom nios system and i have a number of questions

in my system i have an epcs controller and custom interfaces to an asram, dual port ram and custom logic. i have also instantiated an on chip memory (max 20 k). up until now we have not used tightly coupled memory and have tried different methods to bypass the cache through software. however the system is not working properly. we have also tried different configurations for the auto-generated linker script in the system properties for our project in the ide. my questions are as follows :-

1. is it true that the cache can be removed from within the sopc by instantiating tightly coupled memory (it sounds that way from the nios documentation) ? it appears from the documentation that i can run parts of the code within tightly coupled memory and other parts in the other memory devices that i have instantiated. in such a case, are all accesses to the different memory devices cache free ?

2. where can i find more information on how to use custom linker scripts? examples ? i need a bit more information that what is provided in the nios ii software developer’s handbook.

3. when i instantiated tightly coupled instruction memory i noticed that within the sopc builder, the branch that extends from the tightly coupled instruction master only allows a connection to the tightly coupled on chip memory. also within the ide system library for my project, within the system properties settings, for the program memory (.text) i was only able to choose the tightly coupled memory. my question is, if the auto-generated linker script was only able to run the code from the tightly coupled memory (which also seems to be apparent from the sopc tightly coupled instruction master branch limitation outlined above) how can a custom linker script place part of the code in the tightly coupled memory and the rest in another memory device ?

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I&#39;ll answer the parts I can and leave the rest for someone else.

For a /f core, you can remove the data cache but not the instruction cache. Do this by double-clicking on the CPU entry in SOPC builder. If you&#39;re talking about removing the cache at all that&#39;s probably what you want to do anyway. Alternatively you can set the high bit of all memory accesses you want to bypass the cache for (so | 0x80000000) and leave the data cache for everything else.

So you don&#39;t remove the cache by instantiating tightly-coupled memory, the two are separate. Look at the full-featured example to see how to hook up a TCM that you can run code from. It involves connecting the TCM to the regular data master and the tightly-coupled instruction master, since the TCIM can&#39;t write to memory.

When I ran a program out of TCM I had two, an instruction and data memory. In the IDE I assigned .text to the instruction memory and everything else to the data memory.

I don&#39;t know anything about custom linking scripts but I know I&#39;ve seen examples on the forum so a search should turn up some useful information.