Tightly-coupled interface to custom components

I measured 2 clocks for both read and write on a /f without a data cache.

I think the slave is generating a wait state - which is very difficult to avoid on the read cycle!

My thoughts in this area are that the nios need not stall on MM transfers.

For writes simply using a 'posted write' would be enough to allow most writes to complete in a single cycle (a second transfer would have to stall).

For reads it ought, somehow, be possible to cause a 'D' stage stall when the required value is needed instead of an 'A' stage stall.

Both these would need to be options - since they will increase the processor size.

It is worth noting that the 'late result' is actually a 'normal result' - and happens when the resultant value has to go via the register file.

I think non 'late result' instructions use special logic to forward the output of the ALU back to its inputs.