Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorthe "signed" type i/o in vhd file disapear when i try to add my new component
hi every one; i write my own component in vhd and try to add it in qsys, in the component editor, i and my vhd file and click analyze files, it shows 0 errors and 0 warnings. but in the signal...
Altera_ForumHonored Contributor
Honored ContributorSigned/unsigned are perfectly fine for you to use in your HDL design, even at the top level.
But QSYS is pretty rubbish, and only allows std_logic/std_logic_vector ports: Answer: dont use QSYS or just do an internal conversion, as alex suggests above.
