the "signed" type i/o in vhd file disapear when i try to add my new component

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hi every one;

i write my own component in vhd and try to add it in qsys,

in the component editor, i and my vhd file and click analyze files, it shows 0 errors and 0 warnings.

but in the signals & interfaces tab, i can not find the "signed" i/o in vhd files

like:

S_encoder1_Z_reg_out : out STD_LOGIC_VECTOR(1 downto 0);

S_encoder1_AB_for_interpolation_reg_out : out STD_LOGIC_VECTOR(1 downto 0);

S_encoder1_period_counter_reg_out : out signed(31 downto 0);

the "signed" signal does not appear in signals & interfaces tab, the std_logic and std_logic_vector signals are ok

how can i fix this?

should i have to change the signed to std_logic_vector?

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Prefered method to describe external interface for module - std_logic_vector and in implementation you can use casting to or from another type.

Hope this problem not due optimisation when CAD rename or even remove unused ports.

Perhaps if std_logic_vector works for you then you can use workaround :

entity BlaBlaBla is port ( S_encoder1_period_counter_reg_out : out std_logic_vector (31 downto 0 )); end  BlaBlaBla;
architecture v of BlaBlaBla is
signal S_encoder1_period_counter_reg : signed  (31 downto 0 );
begin
  S_encoder1_period_counter_reg_out <= std_logic_vector(S_encoder1_period_counter_reg);
end v;