Honored Contributor
Honored ContributorHi Justin,
> The first problem is that i can't find the up3-flash datasheet(TC58FVT160), http://www.toshiba.com/taec/components/dat...60aft_axb_e.pdf (http://www.toshiba.com/taec/components/datasheet/tc58fvtb160aft_axb_e.pdf) You might want to search the u-boot sources at sourceforge to find a board that supports this flash device and just copy it into your board-specific tree. > So the second problem is where can I find some details using for this u-boot work,such as, > CFG_Nios_CONSOLE,CF G_GBL_DATA_OFFSET,CFG_Nios_TMRBASE,CFG_Nios_TMRIRQ and so on, > because the UP3 munual reference doesn't have this data. Yes, u-boot configuration isn't the easiest task. A nice document for Nios-II would be great ... maybe I'll take a stab at it once I have some spare time ;-) That being said, let me try to help with the following minimum configuration: 1. top-level configuration All of the following are configured via SOPC builder and are in your ptf file with the tag shown in (braces): CONFIG_SYS_CLK_FREQ -the Nios-II clock frequency in hertz (clock_freq) CFG_RESET_ADDR -the Nios-II reset address (reset_offset + the device base) CFG_EXCEPTION_ADDR - The Nios-II Exception address (exc_offset) CFG_ICACHE_SIZE - Size of the icache in bytes or zero (nasys_icache_size) CFG_ICACHELINE_SIZE - Size of icache line in bytes (nasys_icache_line_size) CFG_DCACHE_SIZE - Size of the dcache in bytes or zero (nasys_dcache_size) CFG_DCACHELINE_SIZE - Size of the dcache line in bytes (nasys_dcache_line_size) 2. memory base addresses Define all of these ... set size to zero if not applicable. These should be available in your SOPC builder memory map. CFG_FLASH_BASE - base address of flash CFG_FLASH_SIZE - size in bytes of flash CFG_SDRAM_BASE - base address of SDRAM CFG_SDRAM_SIZE - size in bytes of SDRAM CFG_SRAM_BASE - base address of SRAM CFG_SRAM_SIZE - size in bytes of SRAM 3. memory organization CFG_MONITOR_LEN - the size in bytes reserved for u-boot CFG_GBL_DATA_SIZE - the size in bytes reserved for u-boot's global data (128 will do) CFG_MALLOC_LEN - the size in bytes of the u-boot heap These can be quite confusing, but they let you fine-tune your configuration. Normally, they're all defined relative to the u-boot text base. See the PK1C20.h file for example. CFG_MONITOR_BASE - u-boot text base address (same as the .cfg file) CFG_MALLOC_BASE - base address of heap CFG_GBL_DATA_OFFSET - base address of u-boot's global data CFG_INIT_SP - initial stack pointer 4. required component configuration u-boot needs a uart and a timer. Here's the configuration macros you should use: CFG_NIOS_TMRBASE - base address of the timer used by u-boot CFG_NIOS_TMRIRQ - the interrupt request number used by the timer CFG_NIOS_TMRMS - the timer interval in milliseconds If the timer provides period registers AND the default count is not acceptable to you, you can configure CFG_NIOS_TMRCNT. CFG_NIOS_TMRCNT - value used to load the period registers of the u-boot timer. CFG_HZ - number of hertz per timer tick. This is used by networking code and is dependent on the timer macros above. CFG_NIOS_CONSOLE - Base address of the uart or jtag uart component. CONFIG_CONSOLE_JTAG - Define this when using the jtag uart CFG_NIOS_FIXEDBAUD - Define this when uart is fixed baudrate or with jtag uart CONFIG_BAUDRATE - the initial baudrate (or the fixed baudrate) in bps CFG_BAUDRATE_TABLE - a table of allowed baudrates. This has one entry for fixed rate uart/jtag E.g.: # define CFG_BAUDRATE_TABLE {115200} /* It's fixed */ or# define CFG_BAUDRATE_TABLE {9600, 19200, 115200} /* Allows selection of rate via cli */ I hope this is useful ... configuring u-boot via a gui would be great ... but, good or bad, if you want a very high level of control, editing a configuration file will force you to really know your code. If you have any questions or need additional information, just post or shoot me some email. Best Regards, --Scott
