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originally posted by gl888@Sep 26 2005, 12:16 PM
1. when i created a sopc component(6 bit address, 32b data), the sopc alocate 0xff length of 32 bit memory. --- Quote End ---
Memory map addresses are byte addresses. However, if you're using an "avalon register slave" type of interface, each address in the slave's address bus is a 32 bit register. Therefore 6 address bits = 64 addresses * 4 bytes/address = 256 bytes of memory map used.
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originally posted by gl888@Sep 26 2005, 12:16 PM
2. the order of all registers is the same as the order i claim register in verilog file. for example, the first claimed 32bit register has offset 0, the next one has offset 1. --- Quote End ---
Correct. There's an "io.h" header file that has macros named IORD(), IOWR(), etc. that make dealing with this easier. For example, "int x = IORD(MY_COMPONENT_BASE, 6);" performs a read access on your component with the address bus set to 6, and stores the result in x.
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originally posted by gl888@Sep 26 2005, 12:16 PM
3. what if i have the mix types of register, 1 bit or 8 bit or 32 bit. how could i know the actual offset from the base. --- Quote End ---
First of all, the Avalon buss sees none of that; it only sees the widths of your readdata and writedata ports, which must match. So it doesn't know if there's 32 bits of register behind that or if there's only 1 bit. The address it's going to put on your address port is going to be a 32-bit register address.
To use a physical device metaphor... custom components on the Avalon bus with register addressing (as opposed to memory addressing) look like a physical device with a 32-bit data bus and an address bus that has A2 as its LSB (i.e. the A0 and A1 pins are omitted because all accesses are 32 bit).
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