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Though parallel processing is an option but I doubt achieving 1GHz. You may split up signal path into 4 branches at 250MHz each but there will be dependency especially with filters and I doubt if this practical. I prefer to go as far as 300MHz clock at best thus restricting myself to about 100+MHz sinusoid including signal bandwidth.
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Sure its practical.
I have ~600 Stratix II FPGAs synchronously processing 4GHz of sampled bandwidth across 120 boards, and another ~1000 FLEX10KE FPGAs (yeah, that old) processing another 8GHz (all using 1GHz clock rate ADCs and parallel processing); see p25 of these slides (p27 of the PDF)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)
Not cheap, but practical :)
Cheers,
Dave
Honored Contributor
