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GPIO_0[0]: D25 : bidir: 3.3-V LVTTL : : 5 : Y
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Not quite able to follow all of that, but the quoted line above seems to show that your pins are bidir. This will not work unless connected to devices (like a GPIO) with bidir pins. You earlier stated that you have separate input and output GPIOs. These should have been separately created with inputs and outputs. If you have created a bidir GPIO, go back and undo it. For bidir, there are extra steps you must do to control the direction and it will only cause problems for you now.
With separate input and output GPIOs, you must connect the output pins from the output GPIO to
output pin symbols on the Quartus page, and input GPIO pins to
input pin symbols. These look different from each other (and different from bidir pins). If the pins on the Quartus page do not look different, you must fix it there.
Then, after you run the Quartus compiler, you will get something in the pin-planner that looks like this (these are different pins because it is an excerpt from one of my projects, different purpose, different FPGA, etc., but the concept is the same).
NodeName Direction Location I/O Standard
FLASH_RW_N Output PIN_W32 3.3-V LVTTL
FLASH_WP_N Output PIN_Y30 3.3-V LVTTL
i_PhyInt Input PIN_Y27 3.3-V LVCMOS
i_PhyLinkOn Input PIN_V29 3.3-V LVCMOS
io_PhyCTL Bidir PIN_W24 3.3-V LVCMOS
io_PhyCTL Bidir PIN_W25 3.3-V LVCMOS
If you do not see input, output and bidir, each where they need to be, it will not work.
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