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Altera_Forum
Honored Contributor
Honored ContributorTCP/IP via TSE and Marvell PHY
Hello,
I have the Nios II dev board Stratix II edition. In addition, we have the MoreThanIP Marvell 10/100/1000 Ethernet daughter card that can be stuck on the dev board. I'm looking for documentation and/or reference designs for implementing the complete TPC/IP stack with this setup. The software side probably is the simplest, because Altera provide Nios II drivers for the TSE. However, how to build the system in SOPC and connect TSE to the PHY? The Altera reference design for ethernet uses a GX board with direct connection from the FPGA to the SFPs, and MoreThanIP's ref designs include *their* MAC and not Altera's TSE. Both aren't what I'm looking for. Thanks in advance15 Replies
Altera_ForumDoes the PHY chip answer on the MDIO pins? Is it correctly identified by the embedded software?
- Altera_Forum
have a project a some code that many people writing at www.alterawiki.com
- Altera_Forum
Unless you have an answer to the specific problem mentioned in the original post, it is really no use just pointing to the wiki. This isn't helping.
- Altera_Forum
still not related to the original problem
