Target is broken and needs to be reset

Hi guys, I have an issue with NIOS II (using Quartus 9.1, Stratix III, Micron LPDDR2).

Altera doesn't have built in support for Micron LPDDR2 which uses 10-bit Cmd Address instead of RAS, CAS, WE, ADDR, BA, etc. So what I needed to do was to generate as much as close as possible a DDR2 High Performance Controller II with Altmemphy using SOPC Builder.

Currently, I am modifying all files generated by SOPC Builder regards to the ddr2 controller and incrementally turning it into my LPDDR2 Controller.

So far, I have successfully done the following changes:

1.) Added eight pll clkout for no mimic path feedback mem_clk and mem_clk_n (no issue here regards to compilation)

2.) Added support for two CKE and CS_n for my two-die LPDDR2. (Both signals must be asserted and deasserted the same time, no issue regards to compilation)

3.) Very close to including the 10 bit Command Address bus, just need to propagate it to the AltMemPhy verilog.

Now my issue with NIOS is regards to debugging the custom controller. My NIOS works great without my custom LPDDR2 controller. I normally use the system-console for first level debug by reading the SYSID with it and Hello World as a second level debug.

Whenever I include the custom LPDDR2 Controller so that I can probe out the clocks and control signals using an oscilloscope, I get the error on system console saying the Target is Broken. Well, obviously since my LPDDR2 is not done yet. However I still need to look at how my control signals are working. I simply try to read the SYSID to begin my first level debug but I get that error while doing processor_stop on Systemconsole.