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DBarn22
New Contributor
New ContributorTarget Connection to NIOS II
I have an FPGA design on a MAX10 DECA board. It consists of an outer verilog file with minimal logic mainly pins connecting to a QSYS block, which includes various things including a NIOS II and a...
DBarn22New Contributor
New ContributorMany, many, many times.
I now have this roughly working, I still have timing warnings that need to be sorted. Some of the code was introducing gross slack issues, removing that allowed programming (some/most of the time).
