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DBarn22's avatar
DBarn22
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5 years ago

Target Connection to NIOS II

I have an FPGA design on a MAX10 DECA board. It consists of an outer verilog file with minimal logic mainly pins connecting to a QSYS block, which includes various things including a NIOS II and a...
EricMunYew_C_Intel's avatar
EricMunYew_C_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Did you regenerate your new FPGA bitfile in Quartus and reprogram the new image into your FPGA.