"Taking the SDRAM bridge out of reset"

Hello everyone,

(using DE0-Nano-SoC w/ Cyclone V SoC)

First of, I am relatively new to SoC design and to working with Altera products. I am trying to accomplish a project where I am moving data from the FPGA to the DDR3, and was thinking of using the fps-sdram bridge available. But I am a bit confused. In some places I read info on how it is very necessary to take the FPGA-SDRAM bridge out of reset (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/important_note_about_fpgahps_sdram_bridge)

But in the posts and examples I find online, using the sdram bridge, there is almost no mention of taking the port out of reset. This leaves me a bit confused.

Whats the deal when using the FPGA-SDRAM bridge? Does it require special attention when using it or can it be treated like a normal bridge (set everything up in Qsys and go)

And if it is indeed necessary to initialize the port, is there sample code present, or a standard procedure to follow? Maybe a premade script somewhere (since taking the port out of reset should be a pretty standardised procedure?)

(Because I found a lot of topics on this subject, I will link some projects demonstrating the use of the bridge. Making it easier for people in the future should they stumble across this topic:

https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/writing_to_hps_memory)