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Altera_Forum
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8 years ago

"Taking the SDRAM bridge out of reset"

Hello everyone, (using DE0-Nano-SoC w/ Cyclone V SoC) First of, I am relatively new to SoC design and to working with Altera products. I am trying to accomplish a project where I am moving da...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I stumbled across this explanation, https://www.altera.com/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html?utm_source=altera&utm_medium=newsletter&utm_campaign=facts&utm_content=na_how_can_i_enable_ki_15_08_2016

adding "run bridge_enable_handoff" to the u-boot should take care of it when using SoCEDS13.1 or newer.

EDIT:

RUNNING ONLY THE BRIDGE_ENABLE_HANDOFF WILL NOT WORK IN SOME CASES.

PLEASE REFER TO: http://www.alteraforum.com/forum/showthread.php?t=51200

THIS WORKED FOR ME!

a small remark on what is mentioned in this topic; I ran : 

setenv fpga2sdram_handoff 0x311
saveenv
run bridge_enable_handoff

After this i programmed the FPGA and booted linux.

after this i was able to use the F2S port to write to SDRAM

I also added these lines to my u-boot.scr