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Altera_Forum
Honored Contributor
12 years agoSlacker .. you may have nailed it .
Went back to QSYS and the DMA read master port was conected to the PCIe TX port only and not the NIOS II data master port. This may explain why it is not seen in system.h and the dev list is empty. Can you say what devices appear in the dev list as the list was empty ... ie does the hardware UART and Timer appear in the list. They are not in the design but I doen't see any "open" calls for them list they don't need to be opened ?? Thanks for your help ... Bob