Syntax error in DDR timing scripts?

Thanks for the tip, sadly here is the result:

*********************************************************************

* DDR & DDR2 SDRAM Controller Compiler *

* Applying the constraints for the datapath in the your MegaCore *

*********************************************************************

Error: Evaluation of Tcl script remove_add_constraints_for_ddr_sdram.tcl unsuccessful

Error: Quartus II Shell was unsuccessful. 1 error, 0 warnings

Error: Processing ended: Fri Feb 17 14:44:46 2006

Error: Elapsed time: 00:00:00

------------------------------------------------

ERROR: Open project does not exist. Open an existing project or create a new project.

Opening the project again has no effect.

Is "quartus_sh -t remove_add_constraints_for_ddr_sdram.tcl full_featured" correct?

Now when ever I try to compile my design I get the following fatal error

*** Fatal error: Module: quartus_map.exe Exception: Access Violation

Stack Trace:

016b58e3: qcu_set_assignment() + 0x82e (comp_qcu)

04f93dc0:

End-trace

------------------------------------------

Here is a brief run down of what I have done and what Im trying to do:

I have the 'full featured' 2c35 design from the Cyclone II dev kit (we have 4 kits)

We have attached our own peripherals and removed peripherals we dont need in sopc builder and they all work fine on the dev board

Now I need to build a prototype, which has double the amount of ram. Two ICs, giving me 64Mb 32bits wide. I also want to only use banks 1 and 2 of the cyclone for driving the rams. The dev board currently only uses bank 1, So I figure bank 2 for the second DDR IC.

I start by deleting all the pin assignments. I have a very different setup to the dev board in mind.

Then I run the IP toolbench for the DDR SDRAM Controller V3.3.1 (We have a full Quartus seat, and licences for the IP core and the Nios core)

In step 1: Parameterize I change the following:

Presets: custom

memory bus width: 32

number of chipselects: 1 (I assume this is correct even though I have two chips?)

number of clock pairs: 2 (May make the layout job a bit easier!)

In advanced mode it shows:

Memory size 64Mb

Row address bits: 13

Column address bits: 9

I dont change any other options.

Then in Step 2: Constraints, I assign bytes 2 and 3 to '4T' and '2T' ( 0 is already on '3T' and 1 on '5T' This *should* put the second IC on bank 2.)

Then I hit ok and run step 3: Update.

I then rejiggle the memory map automagically, I change the target board to 'unspecified' so sopc builder is happy and generates the ptf.

I update the 'full_2c35' symbol in my bdf, change the ram pin names because I now have a 32 bit bus etc.

And then I get all these problems trying to compile the device.

Am I better off just removing the DDR part from sopc builder, deleting all the tcl scripts from my project folder and just starting again without modifying a 'full_featured' ram controller? Am I even doing this in the correct manner?

thanks for any help

tom

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A quick update - I removed the ddr part in sopc, and started a fresh one. I also removed all the ddr related tcl scripts from my project folder. Now when I try to generate I get the following errors:

2006.02.17 12:43:54 (*) Making arbitration and system (top) modules.

ERROR:

C:/Altera/quartus51full/sopc_builder/bin/generate_pbm_and_system.pl 35 CALLED (Generate_PBM_And_System)

C:/Altera/quartus51full/sopc_builder/bin/generate_pbm_and_system.pl 29 CALLED ((eval))

C:/Altera/quartus51full/sopc_builder/bin/generate_pbm_and_system.pl 29 CALLED (e_project::output)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_project.pm 1485 CALLED (e_ptf_project::identify_signal_widths)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_ptf_project.pm 272 CALLED (e_project::identify_signal_widths)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_project.pm 1183 CALLED (e_module::identify_signal_widths)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_module.pm 2448 CALLED (e_module_database::identify_signal_widths)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_module_database.pm 648 CALLED (e_module_database::make_linked_signal_conduit_list)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_module_database.pm 725 CALLED (e_signal_junction_database::make_linked_signal_conduit_list)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_signal_junction_database.pm 906 CALLED (e_instance::make_linked_signal_conduit_list)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_instance.pm 1350 CALLED (e_expression::conduit_width)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_expression.pm 3493 CALLED (e_signal_junction_database::remove_child_from_parent_signal_list)

C:/Altera/quartus51full/sopc_builder/bin/europa/e_signal_junction_database.pm 573 CALLED (e_signal_junction_database::remove_child_from_signal_list) WHERE

'_bibl_to_the_adapter_slave_y_2 is not a good signal name' OCCURRED on C:/Altera/quartus51full/sopc_builder/bin/europa/e_signal_junction_database.pm 524

255

Error in processing. System NOT successfully generated.

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I can clear the above error by turning off pipelining in sopc (but my design will now fail its timing) but when I try to compile in Quartus, I get the same fatal error as shown above.

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