Syntax error in DDR timing scripts?

Tom,

DDR SDRAM is pretty complicated stuff. The core provided by Altera stretches (exceeds?) the limits of the static timing analysis tool shipped in Quartus II. That, along with additional placement constraints, make for a pretty complicated build procedure. If you just remember to do one thing, in the future, it could prevent these sorts of issues. There should be a "remove_add_constraints_<component_name>.tcl" file in your QII project directory. Remember to run this, from within Quartus II, prior to performing any sort of changes to the DDR and you&#39;ll be happy(ier).

Cheers,

- slacker