symbols and beats, quick clarification needed

It does multiple cycles, driving the appropriate byte enables.

When going from a wide to narrow it will do cycles with no byte enables asserted!

and could you please comment on this setup for transfering 192b wide stream to SDRAM. channelwidth is 0 and packets are enabled.

Dual clock fifo with 8 bitpersym, 24 symperbeat.

=> timing adapter latency: 1 to latency: 0 added by sopcb

=> data format adapter. 8 bitpersym. 24 symperbeat to 4 symperbeat.

=> sgdma, datawidth 32.

=> SDRAM datawidth 32.

would this be efficient and sensible? i set sgdma datawidth to 32, and enabled packets to ged rid of som errors in sopcbuilder.

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It does multiple cycles, driving the appropriate byte enables.

When going from a wide to narrow it will do cycles with no byte enables asserted!

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thanks, these cycles would be ignored by the sgdma right?