Altera_Forum
Honored Contributor
Honored Contributorsymbols and beats, quick clarification needed
are symbols parallell or serial within a beat?
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13 Replies
Altera_ForumYou need to supply some context ....
- Altera_Forum
okay, i am trying to determine which is the fastes way to send a 192 bit wide datastream from a receiver => dual clock fifo => to sdram using dma.
setup 1: using mm interfaces and 2x fifo and DMA, and splitting the stream into one 64 bit wide and one 128 bit wide "channel". setup 2: using ST interfaces and configuring one fifo and one sgdma for (x bits pr symbol)*(y symbols pr beat) = 192 datawidth. - Altera_Forum
there is no doubt that streaming interface with sgdma is faster.
in streaming interface, there are: one beat per clock, one or some symbols per beat, one or some bits per symbol. the bit width of data signal equals to bitpersym*symperbeat. the bit width of empty signal, which assert when endofpkg is high to indicates how many useless symbols are there in the last beat of a package, equals to ceiling(log2(symperbeat)). - Altera_Forum
thanks. can the sgdma "scatter-gather" from three 64bit sources and put in the sgdma** in one cycle?
** meant sdram - Altera_Forum
you mean using 3 sgdmas? it's a waste of area, and if you do so a 192 bit data will be split into 3 parts stored in different areas of your memory.
I think you can use a data_format_adaptor: 64 bitpersym * 3 symperbeat => data_format_adaptor => 64 bitpersym * 1 symperbeat => sgdam with 64-bit data width. - Altera_Forum
I was thinking about three fifos, and one sgdma to transfering 3*64 bits each beat. altough i doubt it can (no experience with dma's). i will look into data_format_adaptor, but ideeally i would like to be able to transfer the whole 192 bits each clockcycle.
- Altera_Forum
I'm not sure of the write rate you'll get to the SDRAM, but it is unlikely to sustain one 32bit word per clock - although you might get bursts of that.
I don't think you can put a 64bit interface on the SDRAM block? This probably means that you need to build your own fifo. - Altera_Forum
okay i should have thought of that. when i configure the sgdma (that writes to sdram), i can set datawidth to 64 without getting any errors in sopc-builder. does that mean it splits the 64 bits into two writes then?
- Altera_Forum
Not sure, but you might end up with a generic 'bus width adapter',
and, if you aren't careful, a clock crossing bridge. Unfortunataly the sopc builder doesn't tell you when it adds either of these. - Altera_Forum
what would the bus width adapter do? discard all but 32 bit or split the write over more cycles?
