Hello combatants,
After a lot of attempts, tweaks, workarounds and so on, a small but working guideline was compiled. Of course, there will be better solutions like scripts - I am very happy to see more efficient solutions.
Have fun,
niosIIuser
environment: - Windows XP SP3
- Altera Embedded Systems Development Kit, Cyclone III Edition, 3C120
- Quartus 9.0 SP1 and Nios II EDS 9.0 SP1
- Quartus 10.1 SP1 and Nios II EDS 10.1 SP1
first step (prepare the 9.0 sp1 sources) Info: (superloop_simple_socket_server_plus.elf) 269 KBytes program size (code + initialized data).
Info: 130802 KBytes free for stack + heap.
To download and run the application:
1. Make sure the board is connected to the system.
2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the
hardware design.
3. If you have a stdio device, run 'nios2-terminal' in a different shell.
4. Run 'make download-elf' from the application directory.
To debug the application:
Import the project into Nios II IDE. Refer to Nios II IDE Documentation for
more information.
second step (import the files to 10.1) - Install Quartus 10.1 SP1 and Nios II EDS 10.1 SP1 or change the environment variables if necessary
- Download and install the Embedded Systems Development Kit, Cyclone III Edition v10.1.0 (ftp://ftp.altera.com/outgoing/devkit/10.1/cycloneiii_3c120_embedded_v10.1.0.exe)
- Copy the directories “app”, “superloop_iniche_lib” and “superloop_tse_lib” from “superloop_sss_plus_3c120_marvell_90sp1\software_example\superloop_simple_socket_server_plus” to “kits\cycloneIII_3c120_embedded\examples\standard\software\superloop” (do not copy the “bsp” directory)
- Delete the files “display.c” and “display.h” in “ kits\cycloneIII_3c120_embedded\examples\standard\software\superloop\app”
- Open Nios II 10.1sp1 Software Build Tools for Eclipse
- Generate a BSP: File → New → Nios II Board Support Package
- Project Name = bsp
- SOPC Information File name = cycloneIII_3c120_niosII_standard_sopc.sopcinfo (“\kits\cycloneIII_3c120_embedded\examples\standard”)
- Disable “Use Default Location”
- Location = ...\kits\cycloneIII_3c120_embedded\examples\standard\software\superloop\bsp
- CPU = cpu
- BSP type = Altera HAL
- Finish
- Right klick on “bsp” in the Project Explorer → Nios II → BSP Editor...
- Tab “Software Packages” → Enable “altera_ro_zipfs”
- Tab “Drivers” → Disable “tse_mac. triple_speed_ethernet, 10.1, triple_speed_ethernetdriver_hal, 10.1” → Generate → Exit
- File → Import... → Nios II Software Build Tools Project → Import Nios II Software Build Tools Project → Next
- Project Location = ...\kits\cycloneIII_3c120_embedded\examples\standard\software\superloop\app
- Project name = app
- Finish
- File → Import... → Nios II Software Build Tools Project → Import Custom Makefile for Nios II Software Build Tools Project → Next
- Project Location = ...\kits\cycloneIII_3c120_embedded\examples\standard\software\superloop\superloop_iniche_lib
- Project name = superloop_iniche_lib
- Finish
- File → Import... → Nios II Software Build Tools Project → Import Custom Makefile for Nios II Software Build Tools Project → Next
- Project Location = ...\kits\cycloneIII_3c120_embedded\examples\standard\software\superloop\superloop_tse_lib
- Project name = superloop_tse_lib
- Finish
third step (modify files) - Open the “Makefile” in “superloop_iniche_lib”
- Look for “MKDIR := $(shell which mkdir) -p” and exchange it with “MKDIR := mkdir -p” (Propably, there is a better way as this workaround)
- Do the same with the “Makefile” in “superloop_tse_lib”
- Do the same with the “Makefile” in “app”
- Remove “C_SRCS += displays.c” in the “Makefile” in “app”
- Exchange “USER_LED_PIO_8OUT_BASE” with “LED_PIO_BASE” in demo_control.c
- Exchange “CFI_FLASH_64M_NAME” with “EXT_FLASH_NAME”
- Remove “#include "displays.h"” in “simple_socket_server.c”
- Remove lines with “putstr_” in “simple_socket_server.c”
- Setup IP, gateway and network mask in “simple_socket_server.h” in accordance with you network.
- The following changes are some kind of “dirty”. Thanks to “mmTsuchi” and “artyanez” who are Member of the Altera forum
- rename function “int close (int fd)” to “int alt_close (int fd)” in “superloop_iniche_lib/iniche/src/alt_iniche_close.c”
- rename function “int fcntl (int file, int cmd, ...)” to “int alt_fcntl (int file, int cmd, ...)” in ““superloop_iniche_lib/iniche/src/alt_iniche_close.c”/alt_iniche_fcntl.c”
- rename function “int read (int fd, void *ptr, size_t len)” to “int alt_read (int fd, void *ptr, size_t len)” in “alt_iniche_read.c”
- rename function “int write (int fd, const void *ptr, size_t len)” to “int alt_write (int fd, const void *ptr, size_t len)” in “alt_iniche_write.c”
forth step (build and be happy) - Build the “app” with “Build Project”
- Configure the FPGA with “..kits\cycloneIII_3c120_embedded\examples\standard\cycloneIII_3c120_niosII_standard.sof
- Download and run the “app/superloop_simple_socket_server_plus.elf”
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