Streaming DMA transfer from UL

Thanks for the input Ken. I had no idea it was that tricky, but it seems to be working now though. After more digging I found out that the dataavailable line is also de-activating the CSn signal. That's not good, because I am starting my peripheral with a few write operation, and keep the DA line inactive until the data stream starts. Since those write operations are not happening, the peripheral doesn't start and the DMA is not initiated at all. So after changing that, it seems to run stable; but now the NIOS is slowing down by about 30%. Should I make the fifo in the DMA controller a bit deeper to minimize interrupt overhead?