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Honored Contributor
Honored ContributorStrange Ethernet behaviour
We currently have a a design which is based heavily upon the Cyclone 3 FPGA dev kit. However, at this point it is very difficult to return to the Dev Kit to test the software some am hoping someone h...
Altera_ForumHonored Contributor
Honored ContributorThanks for you reply and suggestions.
The Board is connected via a GBit switch to a test network that has very little traffic. The issue appears to be present when connected directly using a cross-over cable too, so is unlikely to be network related. We have made some progress today by changing the timing bits in register 20 of the Phy (Marvel as per DevKit). Originally this is set to 0x82 which enables a timing offset in the Phy for both Tx and Rx. By Changing this to 0x02 (process of ellimination) this turns the Rx delay off. I'm still unsure as to why this corrects the issue (hides), more investigation is needed but at least something positive. Cheers Tim
