Strange clock cycle delay in Custom instruction

http://www.altera.com/literature/an/an188.pdf (http://www.altera.com/literature/an/an188.pdf)

Page 14. You enable your logic with the start bit. If you use a register you can see that on the 2nd rising clock edge your data is latched so on the rising edge of the 3rd clock is when the NIOS latches your result (don't forget it needs to latch your data, so that's your 2 clocks of latency).

So it's not really a problem, you just need one more stage of latency. Even if that start came out earlier, since you have a register you'll never get it down to 1 cycle.

Cheers.