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Altera_Forum's avatar
Altera_Forum
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20 years ago

SRAM interface issue

Hi there, I am making a board based on the Nios Cyclone Edition 1C20 from Altera and have a question on the SRAM interface. I will be i/o limitted and as such do not want to use the Byte E...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

1. Don't connect the byte-enables coming out of the SOPC Builder generated module.

2. Tie the FPGA pins connected to the SRAM chip's byte enables high (or low)...not sure which.

Keep in mind that none of the half word or byte-wide accesses will function, but I assume you already know that.

Alternately, you could take a look at the Asynch. SRAM component and modify its class.ptf file so that it doesn't include the byte enables. [Extremely easy!]

Still another option is to wait for an upcoming document which will cover the creation of your own SRAM SOPC Builder component using the Component Editor (Component Builder).

Regardless of which path you choose, it's easy to solve.

Regarding data cache....only if your SRAM is used for data storage _only_. If code/.text is stored there, then you'd need icache, as well.

Cheers,

- slacker