SRAM Addressing in QSYS

--- Quote Start ---

finally I foud the answare my self:

set address width to 21 in generic tri state controller and detach the less significant bit (bit 0) from the sram addr bus.

--- Quote End ---

address width in generic tri state controller is the byte address arrange of SRAM, not the address bus width. Typically, SRAM has two bits byte-enable input, that's to say, the address bus width + log2(byte-enable width) is the address width of byte.

Therefore, do not connect MLB of the address from generic tri state controller to any wire, let it free.