SPI slave code

I'w started to look into the Qsys SPI in the slave mode again since the issue with inconsistent rx data still hasn't been solved. From using SignalTap, it seems that the data being received/sampled in the SPI shift_reg is quite inconsistent.

It looks like the content of the shift_reg isnt always changing with the falling edge of the spi_clk, which I'm assuming it should.

From the attachment showing SignalTap on the SPI slave rx_holding_reg and shift_reg it can be seen that a single byte (0xBC hex value) is being sent from the external SPI master and the tendency it has to not be sampled correctly in the SPI shift_reg.

At the moment the SPI slave is running on a 75MHz clock, the SPI spi_clk is running @ 1Mhz and the SPI timing is set so that the Clock polarity = 1 and the Clock phase = 1. The Data register width = 8 bits.

Any pointers would be appreciated.