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Altera_Forum
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20 years ago

SPI Slave bug?

Has anybody used the SPI core as a slave device in a NIOS II implementation? If so, have you had relatively frequent data errors? There is no HAL for the SPI as slave, so I'm just using th...
Altera_Forum's avatar
Altera_Forum
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20 years ago

I'm using Quartus II v5.0 Build 168, NIOS II v5.0 Build 73c. The clock speed is 65 MHz, and the SCLK is currently about 1MHz, though we've tried a range from about 44 KHz to about 2 MHz, with no difference in results.

I've found that if I have never loaded the TX register, the master reads back 0xFF, and that if I have loaded it with some byte, that same byte will be read out until I re-load the TX register.

Thanks for the interest. You've gotten the SPI slave to work reliably? I haven't seen anything on this or the Altera forums about anybody using the SPI core as a slave. Everybody's always talking about it as a master. I have no problems at all with my SPI master, which makes this seem kinda weird.