thanks for the altera_avalon_spi.c files..
if u dont mind can u copy paste the
alt_types.h and
altera_avalon__spi_regs.h files..
the thing is i'm dealing with the nios1.. so the method of c programing is also rather different..
there's no usage of IOWR...etc..
currently i can understand the functions.. so if i can at least translate the programing method it would really help..trying to model the sequence of relevent events in the program..
btw.. when i tried interfacing the fpga with and extenal hardware [74MH595 shift register]... the SCLK signal from the FPGA doesn't seem to generate a clockin signal..any comments.. and the MISO is always high.. i've re-checked the pin assignment and no change.. i can only suspect the programin code has something to do wit it....
any issues or advise regarding the SPI core for nios(I) is gladly welcomed..
deeply thankful for any sharing,
eddie
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