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So the DMA controller is setup with a 32-bit width on it's avalon masters but the memories are 64-bit right? Yeah I would assume that the avalon fabric would take care of the width translation. I can't find anything in the documentation that would indicate addressing translation is not performed on burst transfers.
Jake
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Yes, that's what I would expect. Actually I was thinking of making a system
where I use a DMA block to transfer data from the PCIe block to a memory
(in burst mode, seems only possible with 64-bit alignment) and then maybe from this memory to other blocks in 32-bit DMA mode. But then it seems I need another DMA controller that does not work in burst mode ...
Thanks.
Honored Contributor
