SOPC DMA in burst mode

Can you show us a picture of your SoPC system? Some component in the path is not allowing bursts on non-burst boundaries.

Jake

Hello,

thanks for the fast reply. In the example shown I limit myself

to a DMA controller and two 64-bit memories which I control

via a self-made Avalon master (not burst capable, does that matter ?).

The DMA controller actually does not even finish correctly (busy bit

stays on), when I execute a word transfer (in burst mode).

I wonder if it is possible to let the DMA controller fetch

data in 32-bit burst word mode over the PCIe bus or do I always have

to use 64-bit boundaries. In not burst mode 32-bit transfers work, but

then every transfer is a PCIe packet which degrades performance ...

(I'll post this question in a seperate thread)

Kind Regards,

Jon

So the DMA controller is setup with a 32-bit width on it's avalon masters but the memories are 64-bit right? Yeah I would assume that the avalon fabric would take care of the width translation. I can't find anything in the documentation that would indicate addressing translation is not performed on burst transfers.

Jake

From the SOPC HTML file :

altera_avalon_dma v9.1

actualDmaTransactionRegisterWidth 21

allowByteTransactions false

allowDoubleWordTransactions true

allowHalfWordTransactions true

allowQuadWordTransactions false

allowWordTransactions true

bigEndian false

burstEnable true

maxBurstSize 256

minimumDmaTransactionRegisterWidth 13

minimumNumberOfByteTransfers 8191

readAddressMap

readSlaveDataWidthMax 64

useRegistersForFIFO false

writeAddressMap

writeSlaveDataWidthMax 64

deviceFamily UNKNOWN

generateLegacySim false

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So the DMA controller is setup with a 32-bit width on it's avalon masters but the memories are 64-bit right? Yeah I would assume that the avalon fabric would take care of the width translation. I can't find anything in the documentation that would indicate addressing translation is not performed on burst transfers.

Jake

--- Quote End ---

Yes, that's what I would expect. Actually I was thinking of making a system

where I use a DMA block to transfer data from the PCIe block to a memory

(in burst mode, seems only possible with 64-bit alignment) and then maybe from this memory to other blocks in 32-bit DMA mode. But then it seems I need another DMA controller that does not work in burst mode ...

Thanks.

Is it possible for you to post your DMA register configuration as well?

SOPC should be able to handle the 32-64 burst conversions.. but there are specific register settings that need to be configured...

thx

Ok, I just fill in the source & dest addresses and then set

the control register to 0x8C (32 bit mode + go bit + LEEN bit).

In 64-bit mode I get working results with the control register

then set to 0x488

Kind Regards.

Hi,

I was also facing similar problem while using DMA to perform transaction between PCI having 64 bit data width and on-chip memory having 32 bit data width.( Read master of DMA was connected to PCI_Bus_Access module and write master was connected to onchip memory having 32 bit data width. Note that I was using DMA in burst mode.

When I configured DMA to transfer 256 bytes from PCI to onchip at offset 0x100, first 128 bytes were correctly written to CORRECT offset.But then offset was reset to 0x100 and next 128 bytes overwrote previously written data.Thus all bytes were useless.

We came across one work-around for this.( Many thanks to Joe.) We connected on-chip memory to write master of DMA via Clock crossing bridge.Means now avalon slave of clock crossing bridge is connected to write master of DMA and avalon master of clock crossing bridge was connected to on-chip memory. (Now there is no DIRECT connection between on-chip memory and write master.) With this, DMA transaction was successful!

I know Clock crossing bridge is used when slave and master have different clock. But this is just one way we can used it to overcome our problem.

I noticed following points when using DMA in burst mode: ( This is not applicable to non-burst mode)

(1) Read master and write master of DMA must not be connected to slaves having different data width. Means you must not connect write master to slave having 32 bit data width and read master to 64 bit data width. Incase you need to perform DMA transaction between slaves having 32 bit data width and slave having 64 bit data width, please connect 32 bit component via clock crossing bridge. This is one way how you can perform DMA transaction between slaves having different data width.

If you will connect DMA's read and write masters to slaves having different data width and have configured DMA in burst mode, data will not be written/read from/to correct locations.

(2) Control register must be configured to perform transaction based on DMA's full data width.

For example, suppose DMA controller's Read and write ports have been connected to following 3 avalon slaves ( slave having 8 bit and 32 bits must be connected via clock crossing bridge for correct operation as mentioned in 1st point),

Avalon slave with data width = 8 bits,

Avalon slave with data width = 32 bits,

Avalon slave with data width = 64 bits.

In this case, DMA's data width will be 64 bits.

Now even though you wish to perform DMA operation between slave with data width = 8 bits and slave with data width = 32 bits, you must enable DoubleWord (bit 10 in control register) transaction in Control register.If you select, byte transaction (bit 0 in control register), you will get unexpected behaviour.

Please have a look at :

http://www.altera.com/support/kdb/solutions/spr240514.html

(3) Transfer length must be in multiple of DMA's full data width.

Considering above example, transfer length must be in multiple of Double words.(i.e 8,16,24,32,....etc)

If you wish to transfer 17 bytes,then you should configure DMA to transfer 16 bytes and last byte needs to be transferred without DMA use.

Hope this information might be useful to somebody.

Again thanks to Joe for his help.

Regards,

Bhaumik