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Altera_Forum's avatar
Altera_Forum
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20 years ago

SOPC builder 5.0 error

Hi to all,

recently I designed a flash memory controller and when I tryed to add it to the SOPC builder list I got back this error:

Error: command "quartus_map --generate_hdl_interface=C:/altera/kits/nios2/examples/vhdl/niosII_cyclone_1c20/full_featured/ce_temp_directory/AM29LV400B.vhd ce_temp_directory/ce_temp_quartus_project" returned 2

Internal Error: Sub-system: SGN, File: sgn_analyzer.cpp, Line: 1343

Error: Fine dell'entità non consentita; fine tag mancante. (XML)

this happen only with Quartus II 5.0 SP1, infact disinstalling this version and installing the 4.2 version, everything goes Ok.

Does anyone can explain what happen am I in wrong?

Thank you

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    I finally discovered the error!

    It's seams that the SOPC builder 5.0 (Quartus II 5.0 SP1) isn't unable to resolve the assignment of the peripheral if the type of the pins is derived as subtype.

    Look at the below interface:

    port (clk: in std_logic := '0';

    reset: in std_logic := '1';

    read: in std_logic := '0';

    write: in std_logic := '0';

    chipselect: in std_logic := '0';

    waitrequest: out std_logic;

    address: in NIOSAddressBus_Type := (others => '0');

    writedata: in NIOSDataBus_Type := (others => '0');

    readdata: out NIOSDataBus_Type;

    ...

    where the three types are defined in a package and has the below definition:

    subtype FlashDataBus_Type is std_logic_vector(15 downto 0);

    subtype NIOSAddressBus_Type is std_logic_vector(18 downto 0);

    subtype NIOSDataBus_Type is FlashDataBus_Type;

    The only way to make it to works is to replace the type with its definition like below:

    port (clk: in std_logic := '0';

    reset: in std_logic := '1';

    read: in std_logic := '0';

    write: in std_logic := '0';

    chipselect: in std_logic := '0';

    waitrequest: out std_logic;

    address: in std_logic_vector(18 downto 0) := (others => '0');

    writedata: in std_logic_vector(15 downto 0) := (others => '0');

    readdata: out std_logic_vector(15 downto 0);

    This doesn't happen in Quartus II 4.2.

    Thank you.