SOPC + external Vhdl simulation

Ok that worked! the VHDL file communicate with SOPC, thanks!

but now when i run the nios program:

#include <stdio.h>

int main()

{

int n;

while (1)

{

printf("chose an option: \n 1 \n 2 \n 3 \n");

scanf("%d",&n);

printf("choice: %d \n", n);

}

return 0;

}

i see in modelsim that some of the ports of the SOPC system (CORE.vhd) are like disconnected.

component core is

port (

-- 1) global signals:

signal clk50mhz : in std_logic;

signal reset_n : in std_logic;

-- the_pio

signal in_port_to_the_pio : in std_logic_vector (15 downto 0);

signal out_port_from_the_pio : out std_logic_vector (15 downto 0);

-- the_uart

signal rxd_to_the_uart : in std_logic;

signal txd_from_the_uart : out std_logic

);

end component core;

This port are without signal (exept for initialization)

in_port_to_the_PIO, out_port_from_the_PIO, txd_from_the_UART.

But using UART_log e UART_drive i can send and receive information!!!

Why???