Some questions about DMA and FIFO connection

#1 The FIFO will assert waitrequest to apply back-pressure to the fabric (and the DMA)

# 2 There is a shallow FIFO inside the DMA so if the write master is being back-pressured by waitrequest then the read master will stop reading eventually. This will cause the arbiter of the SDRAM to allow other masters in like the CPU for example. Even while the DMA is issuing reads to the SDRAM the arbiter will let the CPU sneak in accesses to the SDRAM due to fairness based round robin arbitration.

# 3 To pop the FIFO the master should read from a constant address (whatever the base address is of the FIFO). If the FIFO becomes empty it should assert waitrequest to avoid underflowing the FIFO.