Honored Contributor
Honored Contributor
after i cycled power leds started blinking fast, as in original design written into epcs (without frequency divider). when i switched back to quartus and jtag chain was scanned from quartus, my signal tap did not run requiring fpga re-programming. after re-programing from quartus via jtag the software is running 4 times slower again... --- Quote End --- When you reconfigure the FPGA via JTAG, the M4K memories do get re-initialized. However, it sounds like you have setup your Nios II boot address so that it points to the EPCS device. This means that whenever the Nios II processor comes out of reset (such as when the FPGA is reconfigured), it's going to run the boot copier out of the EPCS device all over again. But since you just reconfigured the FPGA with a Nios II running 1/4 the speed, it's going to run the software 4 times slower. When you power cycle, the FPGA is automatically configured with the image stored in the EPCS (the Nios II with no clock divider). This processor then boots from the EPCS, runs the boot copier, jumps to RAM, and the LED blinker runs again at full speed. Hope this helps. Nate Knight Altera
