Software runs w/o reloading on changed FPGA design

Another observation today - I went to SOPC Builder to change the timing on my external SRAM memory configured as a User Logic on a Avalon tri-state bus. I have re-generated nios microcontroller in SOPC builder. After this was done, I closed SOPC Builder app and went back to Quartus, opened main schematic page, updated nios symbol, saved the file and re-compiled my project.

I did NOT program my FPGA but the Signal Tap had "Ready to acquire" status. So I tried to acquire data and everything worked fine, like no of my timing changes took effect (of course, they were not sent to the chip!).

Very strange - Quartus did not recognise the design has changed and the chip should be reprogrammed before a datascope can be acquired.

Is this a bug or a feature? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif