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originally posted by kerri@Jul 12 2004, 12:15 PM
i **think** (i could be wrong) that it is because when it is running fast, it is running out of flash. when you download a design, that design starts running (not the one in flash). when you powercycle the board, it starts out of flash again. --- Quote End ---
I am not sure if you get my question right... I asked:
<div class='quotetop'>QUOTE </div>
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"Why re-loading fpga via JTAG did not reset software/ram area of the fpga device?"[/b]
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I am not surprised with the fact that when I am running a design with a frequency divider the code is running slower - it is kind of obvious. I am suprised that changing fpga design did not force on me code recompilation and reloading.
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