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Altera_Forum's avatar
Altera_Forum
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13 years ago

Simulating Nios system as a module

I searched for “simulation” in the Nios forum and read all the related results I could find. I also read Altera’s “AN-351 – Simulating Nios II Embedded Processor Designs.” I am still confused.

My goal is behavioral simulation of a system written in SystemVerilog that contains a Nios processor as a module. The simulation environment is ModelSim.

The project hierarchy looks like this: 

Top level module
	Nios system
		Parts of Nios system (memory, etc)
	Unrelated module 1
		Submodules
	Unrelated module 2
	...

I would like to simulate the top level module to make sure the whole project (including Nios) is working. My Nios system runs from internal memory and has a memory initialization file so that it comes up running my code.

AN-351 seems to only cover simulating a Nios/Qsys system itself. In my case the modules labeled “unrelated” are not part of the Qsys system.

I started down the path of simulating it like any system written entirely in SystemVerilog. Then, from the Qsys-generated files I added simulation/my_nios.v. As expected, that gives me an error for each of the 40 missing submodules.

I can add those manually by hand, but that will take some time. Before I go too much farther down this path, is there something wrong with my approach? I originally expected there to be a smooth process for what I want to accomplish.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I can add those manually by hand, but that will take some time. Before I go too much farther down this path, is there something wrong with my approach? I originally expected there to be a smooth process for what I want to accomplish.

    --- Quote End ---

    Read this tutorial:

    http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

    The Qsys version of the design shows how to use the Modelsim setup script to configure the simulator for your custom design.

    Since your simulation will be tested by running code on the processor, the default testbench with clock and reset generator would be adequate for your design. Hence, you do not need to customize the testbench as the tutorial shows. However, you might want to implement a custom testbench if you want to change the I/O that the NIOS system sees.

    For example, when you want the simulation to stop, you could assert an I/O pin. The testbench can monitor that pin, and then issue a stop command.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you for the reply. Unfortunately, I am not savvy enough with ModelSim and tcl to work with that advice easily. I have spent the last few hours on it and am still struggling. Until recently it was especially time-consuming because Altera’s scripts corrupt my existing testbench code (they add a modelsim.ini file to the project that breaks existing simulations by steering ModelSim away from them).

    As I mentioned, the Nios system is a module inside a larger system written in verilog. That larger system had a testbench in place before I created the Nios module, and I want to continue to simulate everything at once. This is the original ModelSim simulation script: 

    
#  Clean the transcript window
.main clear
#  delete the work directory and re-create the work library
if  { vdel -lib work -all }
vlib work
# Compile files
vlog -incr ../tb/tb_sketchpad.sv
vlog -incr ../src/DE0_Nano.sv
# Run simulation
vsim -l ./transcript +notimingchecks -t ps work.tb_sketchpad
rad hex
view structure
view signals
do wave.do
run -all

    Before adding the module with the Nios system, that was working fine. Then I added the Nios system. Based on the instructions in the document you referenced, I made changes so that it looks like this: 

    
#  Clean the transcript window
.main clear
#  delete the work directory and re-create the work library
if  { vdel -lib work -all }
vlib work
# Extra stuff for Nios goes here---------------
set QSYS_SIMDIR "../nios/simulation"
source ../nios/simulation/mentor/msim_setup.tcl
dev_com
com
vlog -incr "../nios/simulation/my_nios_spi.v"
----------------------------------------------
# Compile files
vlog "../tb/tb_sketchpad.sv" -work tb_sketchpad
vlog "../src/DE0_Nano.sv" -work DE0_Nano
# More Nios stuff------------------------------
set TOP_LEVEL_NAME tb_sketchpad
elab
# ---------------------------------------------
vsim -l ./transcript +notimingchecks -t ps work.tb_sketchpad
rad hex
view structure
view signals
do wave.do
run -all

    I had to put the testbench compile in the middle for two reasons. First, tb_sketchpad needs to be defined before I use it for TOP_LEVEL_NAME. Second, the “work” location is defined by Altera’s scripts, so I have to wait for them to define it so I can use it as a reference.

    However, that still isn’t working. Currently I get an error on the vlog…tb_sketchpad line:

    [Failed to access library ‘tb_sketchpad’ at “tb_sketchpad”. ]
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Type 'vmap' in Modelsim to see where the libraries are being mapped to.

    The Qsys synthesis script 'takes over' some Modelsim mappings, and hard-codes paths relative to ./libraries/, which is pretty annoying (as I comment in the appendix).

    The trick is to either live with where Qsys wants to define the work folder, or define a new library for your application. For example, you could 

    # change directory to where you want your sketchpad library
vlib sketchpad_lib
vmap sketchpad_lib /sketchpad_lib
vlog -sv -work sketchpad_lib ../tb/tb_sketchpad.sv

    Now your code will be in its own library, not the work library.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I tried following your example to use multiple libraries, but I ended up with similar errors as before. Sticking to one library seems easier to wrap my head around. I made some progress, but I still do not have it working. This is the current state of my ModelSim script: 

    
#  Clean the transcript window
.main clear
#  delete the library directory if it exists
if  { vdel -lib libraries -all }
# Extra stuff for Nios goes here---------------
set QSYS_SIMDIR "../nios/simulation"
source ../nios/simulation/mentor/msim_setup.tcl
dev_com
com
vlog -incr "../nios/simulation/my_nios_spi.v"
----------------------------------------------
# Compile files
# These two lines attempt to compile my existing code into the work location defined by Altera
vlog -incr "../tb/tb_sketchpad.sv"
vlog -incr "../src/DE0_Nano.sv"
# More Nios stuff------------------------------
set TOP_LEVEL_NAME tb_sketchpad
elab
# ---------------------------------------------
# Run my testbench
vsim -l ./transcript +notimingchecks -t ps tb_sketchpad
rad hex
view structure
view signals
do wave.do
run -all

    If I comment out the Nios module in my FPGA design, that ModelSim script will actually run the rest of the design. In that sense it is progress compared to nothing working. However, it still does not work with the Nios module actually instantiated. The script makes it all the way to the vsim command, then starts spitting out errors like this: 

    
#  ** Error: (vsim-3033) ../nios/simulation/my_nios_spi.v(456): Instantiation of 'my_nios_spi_nios2_qsys_0' failed. The design unit was not found.
#          Region: /tb_sketchpad/m_nano/m_nios
#          Searched libraries:
#              C:\Users\afaulstich\Documents\FPGA\DE0_Nano_sketch_pad_NiosSPI\sim\libraries\work

    If I type “vmap” into the ModelSim console I see that the design unit does have a mapping in place: 

    
#  "my_nios_spi_nios2_qsys_0" maps to directory ./libraries/my_nios_spi_nios2_qsys_0/.

    It looks the same for all the other errors; they have mappings in place, but the files are not being recognized. It looks like vsim is searching for the mapped files in ./libraries/work instead of ./libraries.

    Is there a simple way to correct that?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Is there a simple way to correct that?

    --- Quote End ---

    I'm not sure about it being 'simple', but you could edit msim_setup.tcl and edit that file to stop it from using an absolute path. Unfortunately, you'll have to edit the file each time you generate a Qsys system.

    I find the use of absolute paths frustrating as well.

    Actually, perhaps the best option is to use msim_setup.tcl purely as a reference script. Create a new script and compile the libraries as shown in that script, but into a new library, say qsys_library. That way you control everything. If you change the Qsys system, then review the changes to msim_setup.tcl and edit your own simulation script accordingly.

    Cheers,

    Dave