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I can add those manually by hand, but that will take some time. Before I go too much farther down this path, is there something wrong with my approach? I originally expected there to be a smooth process for what I want to accomplish.
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Read this tutorial:
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial The Qsys version of the design shows how to use the Modelsim setup script to configure the simulator for your custom design.
Since your simulation will be tested by running code on the processor, the default testbench with clock and reset generator would be adequate for your design. Hence, you do not need to customize the testbench as the tutorial shows. However, you might want to implement a custom testbench if you want to change the I/O that the NIOS system sees.
For example, when you want the simulation to stop, you could assert an I/O pin. The testbench can monitor that pin, and then issue a stop command.
Cheers,
Dave
Honored Contributor
