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Altera_Forum
Honored Contributor
11 years agoThank you for that information; the design is now fully constrained, and there are no failing paths in the partition containing the Ethernet Subsystem, however, I am still unable to connect to the server.
Edit: I have found that forcing the connection to run at 10Mbps, I am able to connect to the server. I think that there may be an issue with how I set up my clock multiplexer. I currently have 2 two-input multiplexers; one that chooses between 125 and 25, and a second that chooses between the former selection and 2.5. I will attempt to make a single 3-input clock mux and see if that makes a difference. Update: Stratix IV does not allow 3 input clock muxes, thus I seem to be forced to use a PLL with 1/1 which leads to inconsistent PLL crosschecking. Any ideas on how to overcome this limitation?