Forum Discussion
Altera_Forum
Honored Contributor
9 years agoPay attention that in the reference design the CPU Data & Instruction masters are both connected both to the flash and to the SDRAM.
I saw design failing 'cause porting the design to a new version or a new board, those connections were not properly done. To also exclude HW issue on your specific board (if not the PHY), you can map all into an On-chip memory RAM if you've enough free. I also report here from previous page: - if you've limited time SOF you shall keep the USB Blaster connected and do not close the pop up that comes once you program the device. - be sure to have given right timing constraints to your RGMII IF and that your timing are closed.