Simple question regarding memory, just curious.

What anakha mean is that Nios/Avalon system is based on byte addressing; then a 32bit word at address A is actually the same as 4 bytes at addresses A+0, A+1, A+2, A+3.

During 32bit memory accesses, the lower two bits of address are discarded and the 32bit word is aligned on multiple of 4 addresses. So you get distinct data for addresses 0, 4, 8, 12, 16 etc. While if you read back at 1, 2, 3 you get the same as address 0, like in your case.

On the other hand, if you use the IORD and IOWR macros, the native width of the bus is considered: for a 32bit memory device IORD_32DIRECT at address A is equivalent to IORD at address A/4.

For more comprehensive information refer to the Nios software developer handbook, ch. 9.