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Altera_Forum
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19 years ago

Signal Tap

Hi, I have some problems with the Signal Tap Logic Analyzer. Sometimes it works pretty nice and I can observe the selected signals. But sometimes it smashes my design completely, if only ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Hi Maria

First, I'm sorry for my bad english...

- What happens, if you re-change the nodes back to the state before?

Very IMPORTANT:

- Are you shure that your design is really synchronous?

Some severe asynch path in your design will sometimes produce exactly this situation: every time you re-compile your design (without any change !) the result is not predictable. This is not an failure of Quartus. Your design in FPGA must be as synchronously as possible.

I had that problem while re-engineering an completely asynch APPLE II into synch FPGA. Now I have more grayed hair after finishing that project succesfully... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/rolleyes.gif

Jens