Honored Contributor
Honored ContributorMy CPU (NIOS II/s 1.1 in a Cyclone EP1C12/7) uses:
- SRAM (256k x 32) on Avalon Tri-State - 3 different interfaces to user logic on Avalon Tri-State - 1 SDRAM-Controller sharing Address- and Databus (16MB) - 15 additional devices (ports, uart, spi) connected to Avalon-Bus - 2 further Bus-Master accessing SRAM and SDRAM (DMA and PCI-Bus) Meanwhile it runs; after updating SDRAM-component from version 5.0 and decreasing CPU-clock down to 50MHz (Timing Analyzer says fmax=50,8 MHz). An interface to Ethernet (LAN91C111) is also connected to Avalon-Tri-State, but not yet tested. Booting is done via EPCS which also starts a small loader. The final firmware runs in SRAM, which will be loaded via PCI-bus -> Avalon-Master -> SRAM. With SOPC-builder 1.1 you have to manually edit the .pdf file, to get shared write_n and read_n signals. eltonlaonong, I use SRAM to get the performance and SDRAM to get the buffer size I need. Not sharing signals would allow you to do things real parallel (e.g. DMA transfer parallel to processing). But the pins .... mountain8848, encouraged enough? Mike
