Sharing access to SDRAM between NIOS and hardware

If you put an Avalon MM master interface on your verilog block it can use that to access memory that can be also be accessed from the NIos, the Avalon 'bus' interface logic will hande arbitration between the two masters.

For on-chip memory blocks you can dual-port them between a nios cpu tightly-coupled data block and the avalon bus - this gives the cpu faster access and avoids any issues with the data cache 'interfering' with IO accesses.