Shared pins on Avalon bus devices

I have a problem with SRAM chip and FLASH chip sharing tri-state address/data bus.

I have configured my custom board and ported flash programmer. I have declared FLASH chip as AM29LV641DH with designator U6 on my board. In the board Quartus design I see correct pinout for tri-state bus:

- external_memory_address,

- external_memory_data,

- ext_memory_readn,

- select_n_to_the_flash_memory,

- write_n_to_the_flash_memory.

Do not quite get it why they use a different convention of naming write and read signals, but maybe I will figure it later http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

Now, in my system design using this previously configured board, I added tri-state bus, ext_flash memory which showed up correctly as U6, and a user logic module to my SRAM 16-bits chips on the same bus.

After nios2 cpu symbol was regenerated I got following signals:

- chipselect_to_the_SRAM_bank1 (strange anyway, was expecting chipselect_n!)

- ext_memory_bus_address

- ext_memory_bus_data,

- ext_memory_bus_readn,

- ext_memory_bus_writen,

- select_n_to_the_ext_flash,

- write_n_to_ext_flash.

What is the difference between ext_memory_bus_writen and write_n_to_ext_flash? I have this signals shared on my tri-state bus. How to configure flash chip to share commong ext_memory_bus_writen signal for its write operations?

Also, on my 16-bit bus I have two (active low) signals: low_byte and high_byte. How to configure them with "byteenablen" Avalon signals?