Shared Bus

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originally posted by mesh_guys@Jan 12 2006, 10:36 PM

i'm trying to make a shared bus between 2 niosii cores on a stratix ii fpga. basically, i have a streaming application that does some processing on the first core and then passes the data to the second core for further processing and output. i can get this to work if i just use a shared memory component between the two processors.

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Yes, that&#39;s probably the most natural way to do that for Nios II...

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originally posted by mesh_guys@Jan 12 2006, 10:36 PM

since this is for a research project however, i also need to make it work using a simple shared bus between the two processors. i call it a shared bus because it needs to be scalable to 3 processors and beyond (once we go past 2 ps, there should be contention on the bus).

does anyone have some suggestions on how i should go about doing this?

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If I understood, you want to build a multiprocessor system where there is a shared bus where all the CPUs contend for the shared memory... Basically if you connect all the CPU to an onchip memory with a single port you probably get the contention you want for the access to the shared data because SOPCBuilder will build an arbiter to resolve the contention to the memory from all the CPUs...

However you&#39;ll probably not get everything you want because istruction fetches and local data will probably go on other paths (SOPCBuilder basically generates a crossbar switch to connect CPUs and peripherals/memories...)

Paolo