Share variables between verilog file and niosII application file(.c file)

I am really confused.. Unable to handle a simple thing, please help me out. Kindly refer the document attached that shows my QSYS implementation. It shows system contents, memory address map and also the slave address issue which i am facing.

I modified the slave template file (.tcl)to have only one register. i also tried to increase the bits for slave address, but observed that reg count has reduced to 1 as i expected but even after changing the address field number[3..0], it doesn't get reflected in qsys. it still remains the same.

In HDL i increased the range as "input [15:0] slave_address;". I declared the variable "SharedRam" in HDL as reg [DATA_WIDTH-1:0] SharedRam[10];

I am unable to figure out at what address the "SharedRam" variable is stored in onchip memory. In which file, will i come to know its address.

In HDL i am trying to store value 5 at 0th location of SharedRam variable by using SharedVar[0] <= 5; I hope this fine.

In NiosII I have declared one 4 byte variable : unsigned int uiVar[10] = {0};

and then attempting to read the onchip memory : uiVar[0] = IORD(ONCHIP_MEMORY2_BASE, 20); (ONCHIP_MEMORY2_BASE is 0x20000)

I verified the contents of uiVar[0], and found it is not equal to 5 which i am expecting.

The address of this variable as per niosii_objdump file

000201f8 g O .bss 00000028 uiVar

Kindly help me write to known address in HDL and then use niosII to read the data from the same location.

if the address is known, it is of help.

Similarly later on i will try other way round such that, i will write to a memory location in NiosII and read the same memory location from HDL.

thanks

-Jagdish